DREQE=0, DCLRM=0, MBW=0, CURPIPE=others, REW=0, BIGEND=0, RCNT=0
D0FIFO Port Select Register
| CURPIPE | FIFO Port Access Pipe Specification 0 (0000): DCP (Default control pipe) 0 (others): Setting prohibited 1 (0001): Pipe 1 2 (0010): Pipe 2 3 (0011): Pipe 3 4 (0100): Pipe 4 5 (0101): Pipe 5 6 (0110): Pipe 6 7 (0111): Pipe 7 8 (1000): Pipe 8 9 (1001): Pipe 9 |
| Reserved | These bits are read as 0000. The write value should be 0000. |
| BIGEND | FIFO Port Endian Control 0 (0): Little endian 1 (1): Big endian |
| Reserved | This bit is read as 0. The write value should be 0. |
| MBW | FIFO Port Access Bit Width 0 (0): 8-bit width 1 (1): 16-bit width |
| Reserved | This bit is read as 0. The write value should be 0. |
| DREQE | DMA/DTC Transfer Request Enable 0 (0): DMA/DTC transfer request is disabled. 1 (1): DMA/DTC transfer request is enabled. |
| DCLRM | Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read 0 (0): Auto buffer clear mode is disabled. 1 (1): Auto buffer clear mode is enabled. |
| REW | Buffer Pointer Rewind Note: Only 0 can be read. 0 (0): The buffer pointer is not rewound. 1 (1): The buffer pointer is rewound. |
| RCNT | Read Count Mode 0 (0): The DTLN[8:0] bits (CFIFOCRT.DTLN[8:0], D0FIFOCRT.DTLN[8:0], D1FIFOCRT.DTLN[8:0]) are cleared when all of the receive data has been read from the DnFIFO.(In double buffer mode, the DTLN bit Value is cleared when all the data has been read from only a single plane.) 1 (1): The DTLN[8:0] bits are decremented each time the receive data is read from the DnFIFO. (n = 0, 1) |